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[SCM] jcyf

Description: 本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。-The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to SPCE061A Singlechip for process control and scheduling core mission FPGA for external expansion, internal self-system bus, address decoding using the entire translated code approach. DDS has built internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal.
Platform: | Size: 178176 | Author: 郑坤 | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: 这是quicklogic公司的直接频率合成（DDS）Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
Platform: | Size: 22528 | Author: jinzhoulang | Hits:

[assembly language] EXPT84_DAC2ADC

Description: FPGA+DA转换,ALTERA公司FPGA与DA实现,DA转换功能!-FPGA+ DA conversion, ALTERA company FPGA and DA realize, DA conversion!
Platform: | Size: 16384 | Author: 19820521 | Hits:

[Embeded-SCM Develop] NIosIIStart

Description: NIosII软处理器快速入门,ALTERA FPGA的NIOSII入门指导-Quick Start NIosII soft processor, ALTERA FPGA s NIOSII Getting Started guide
Platform: | Size: 617472 | Author: leedong | Hits:

[VHDL-FPGA-Verilog] AD9852

Description: 数字频率合成器芯片AD9852 的配置文件，HDL级的Verilog代码-DDS chip AD9852 profile, HDL-level Verilog code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] FM-ok

Description: VHDL编写的驱动DDS，ad9850的程序，用于产生FM波-VHDL driver prepared DDS, ad9850 procedures used to produce FM wave
Platform: | Size: 318464 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] shuzhijietiaoqu

Description: 基于FPGA的全数字调制解调器设计实例，包含有Matlab程序和Quartus程序-FPGA-based all-digital modem design example, contains the procedures and Quartus program Matlab
Platform: | Size: 656384 | Author: | Hits:

[Other] fenping

Description: FPGA里面的分频器相关资料-FPGA divider inside information
Platform: | Size: 690176 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] veriloghdl

Description: 来自精益求精的德国人讲授的VERILOG课件，想接触FPGA/CPLD开发的人是必看的课件。
Platform: | Size: 4944896 | Author: 王方 | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[SCM] DDS-320-func

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。
Platform: | Size: 460800 | Author: hangyinli | Hits:

[VHDL-FPGA-Verilog] ddswase

Description: dds信号发生器，可以产生任意频率的正弦波，发波和谐波.已经编译通过-dds signal generator, can generate any frequency of the sine wave, the waves and harmonics. has been compiled through
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] msp430_jtag_nios

Description: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Platform: | Size: 56320 | Author: danielmu | Hits:

[Other] DDSmsk

Description: 基于FPGA+DDS的MSK数字调制源设计 C语言控制DDS-Based on FPGA+ DDS of the MSK digital modulation source to control the design of C language DDS
Platform: | Size: 1024 | Author: 鹏鹏 | Hits:

[VHDL-FPGA-Verilog] ByteBlasterII

Description: 介绍ByteBlastrII(FPGA下载电路接口)的电路设计,按照电路图自己设计,已经试过,能用.好不容易找来的.Altera原装下载线卖1K多呢-Introduction ByteBlastrII (FPGA download circuit interface) circuit design, in accordance with circuit design, has been tried, can be used. Finally got the. Altera download original line does sell more than 1K
Platform: | Size: 122880 | Author: sun huaiming | Hits:

[VHDL-FPGA-Verilog] 20

Description: FPGA语音通信平台设计实例哦-FPGA platform for voice communications design example Oh
Platform: | Size: 55296 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilog] 19

Description: FPGA信号调制通信系统设计实例-FPGA signal modulation communication system design example
Platform: | Size: 27648 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilog] ddsyixiang

Description: dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated
Platform: | Size: 1720320 | Author: 刘明吉 | Hits:

[VHDL-FPGA-Verilog] fpga-fpdpsk

Description: FSK/PSK调制顶层文件 ，正弦波模块 ，正弦波模块初始化文件 ，振幅调整及波形选择模块 ，频率显示值地址产生模块 ，频率步进键核心模块 ，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the frequency of the displayed value address generator module, the frequency of stepping key core modules, bouncing the elimination of circuit
Platform: | Size: 27648 | Author: libing | Hits:
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